The present invention relates to an improvement to electronic synchronizing circuits designed to protect them from instability.
One well known method to synchronize a data signal to a control pulse signal without fixed phase relations between them makes use of flip-flops. A flip-flop is a two stable state electronic circuit having the ability to change from one state to the other on application of a control pulse or "clock pulse." The change in the state of the flip-flop takes place on the leading or the trailing edge, of the so called "sampling edge," of the clock pulse according to the type of flip-flop employed. For each flip-flop type, recommended operating conditions indicate a minimum time preceding and following the middle of the sampling edge which constitutes a critical period in which the received signal on an input must not change in state. Experience shows that, when the signal to be synchronized changes state during this critical period, the clock pulse may present insufficient power to set the flip-flop properly, thus, providing an output which is held in the unstable state. Some tests have measured the duration of this unstable state, which for a flip-flop having a typical switching time of 10 to 20 nanoseconds, may reach several thousand nanoseconds. Now in many fields, especially in that of computers, it is important that the output signal is stable at the time it is examined.
A mathematical study of this phenomenom carried out at the Washington University (Technical Report No. 15, November 1969) has estimated that the probability of the output voltage of a flip-flop being found outside the unstable region after a time t is a function such as 1-e t/.tau.(.tau. being a time constant characteristic of the employed flip-flop). Therefore, a generally selected solution consists of enabling the output information of the flip-flop only after a time T after which the probability of being in an unstable state is acceptable. However, a disadvantage of this solution is the systematic delay of the information generated, whereas the probability that the change in the state of the signal to be synchronized, on one hand, takes place within the critical period and, on the other hand, involves the instability of the output state of the flip-flop, is low.